1. Technical Field
The present invention relates to a clock signal outputting method, a clock shaper and electronic equipment using the clock shaper, and more particularly relates to a clock signal outputting method, a clock shaper and electronic equipment using the clock shaper specifying the operation of a fixed oscillator provided in the clock shaper.
2. Related Art
A network clock signal distributes a common frequency into the network and synchronizes the network. A reference clock signal is distributed to each slave station from a master station or quasi-master station of the network. Transmission and reception are performed in each slave station based on a received clock signal timing-extracted from data received from the transmission path of the network.
Incidentally, when a line fault occurs in the network, a slave station cannot normally receive data from the transmission path, and cannot reproduce the received clock signal. In this case, the slave station cannot transmit and receive until the line fault recovers. In order to prevent this, a clock supply device is provided in the slave station to synchronize with the reference clock signal outputted from the master station, and transmission and reception are performed based on a standby clock signal outputted from this clock supply device. In addition, when a clock signal is lost (missing) within a certain time from the received clock signal or a standby clock signal, transmission and reception are performed based on a clock signal outputted from a fixed oscillator provided in the slave station.
A clock shaper using a Phase Locked Loop (PLL) circuit is used in a transmission device constituting a network communication system. Two selecting parts are provided on a pre-stage of the clock shaper. One selecting part receives inputs of a received clock signal and a standby clock signal, and selects either clock signal. The other selecting part receives inputs of a received clock signal or a standby clock signal and a clock signal outputted from the fixed oscillator, and selects either clock signal.
Japanese Unexamined Patent Publication No. H10-65536 and Japanese Unexamined Patent Publication No. 2001-244812 disclose a device receiving inputs of two clock signals and outputting either clock signal to a PLL circuit. Japanese Unexamined Patent Publication No. H10-65536 discloses suppression of frequency variation in the output from a PPL circuit in a clock signal switching operation by outputting a self-running clock that is always synchronized with a selected clock outputted from the clock signal switching circuit to the PLL circuit from a self-running control circuit provided between the clock signal switching circuit and the PLL circuit when switching the clock signal due to a short break. In addition, Japanese Unexamined Patent Publication No. 2001-244812 discloses that, when switching from a first clock signal to a second clock signal, a switching device provided on an input side of the PLL circuit switches a clock signal in phase with the first clock signal outputted from an oscillator, and then switches from the clock signal to the second clock signal when the difference in phase between the clock signal outputted from this oscillator and the second clock signal becomes lower than a predetermined value.
In the clock shaper according to the above-mentioned art, if a fixed oscillator is provided against a line fault, when the fixed oscillator is always kept oscillating, the received clock signal or standby clock signal (input signal) and the clock signal outputted from the fixed oscillator are inputted into the selecting part. As such, there is a problem in that phase noise is generated in the signal outputted from the selecting part when the frequency of the input signal differs from that of the clock signal outputted from the fixed oscillator.
The present invention has been achieved to solve the above problem, and one object is to provide a control method, a clock shaper and electronic equipment using the clock shaper, that are capable of performing quick synchronized compensation without generating any phase noise in a signal outputted from the selecting part and even when synchronization is not performed by occurrence of a fault in the input signal.